The continuous advancement of semiconductor technology results in ever increasing integration density of semiconductor devices. The critical dimension (CD) of semiconductor devices is getting smaller. This requires greater transistor performance.
In transistors, because the polysilicon gate exhibits relatively high resistance, metal materials have been used as a gate material. The low resistance of metal gate improves transistor performance. The CMOS transistor metal gate is often formed using a gate last process to prevent the metallic material of metal gate from inadvertently affecting the overall structure of transistors.
As shown in FIG. 1, a conventional gate last process includes: forming a dummy gate (such as polysilicon) on a semiconductor substrate. After the source/drain regions 13 are formed, a dielectric layer 11 is formed on the substrate and the dummy gate is removed to form a gate trench 12 in the dielectric layer 11. Subsequently, as shown in FIG. 2, metallic material fills the gate trench 12 to form a metal gate 15.
As shown in FIG. 1, in order to prevent the metal atoms of metal gate from diffusing into the dielectric layer 11 to degrade the performance of the subsequently formed semiconductor device, before filling metallic material into the gate trench 12, a diffusion barrier layer 14 is formed on sidewall surfaces of the gate trench 12 to reduce diffusion of metal atoms from the metal gate 15 into the dielectric layer 11.
However, conventional diffusion barrier layers become insufficient to meet demanding requirements of semiconductor devices. Hence, it is desirable to provide semiconductor devices and formation methods to reduce or eliminate the diffusion of metal atoms.